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systemverilog
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OvertureMMXXI/HDL-RepoBench-Sample
Preview
•
Updated
May 6
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75
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1
AbiralArch/hardware-cvdp-examples
Updated
Aug 1, 2025
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24
AbiralArch/hardware-verilogeval-v2
Viewer
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Updated
Aug 1, 2025
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471
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35
AbiralArch/hardware-shailja-vgen
Viewer
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Updated
Aug 1, 2025
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87
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16
AbiralArch/hardware-cvdp-complete
Updated
Aug 1, 2025
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204
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1
Arrakark/scalared_guidelines
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Updated
Dec 8, 2025
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7.23k
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12
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1
Zanehpn/MHRC-Bench
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Updated
about 2 hours ago
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47.2k
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77
weiber2002/ICRTL
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Updated
Jan 27
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6
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27
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1
VN-26/rtl-llm-dataset
Updated
Mar 30
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22
henryen/hwe-bench
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Updated
Apr 23
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834
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834
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1
ananymous75/hier-sva-ds
Updated
May 6
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19
AnonymousHierSVA/HierSVA
Updated
Jun 15
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279
vyomaalabs/verixa-dataset
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Updated
May 30
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105k
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46
violinwang/specpss-benchmark
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Updated
Jul 8
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52
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16
aashay96/scientific-posttrain-rtl-formal-eval
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Updated
Jul 17
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31
rtl-debug-bench/rtl-debug-bench
Updated
18 days ago
•
42
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2
beatsprom/semiconductor-rtl-verilog-chip-design-2026
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Updated
Sep 7
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1k
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109
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2
aditigupta/EquivSVA
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Updated
Sep 23
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480
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104
HPAI-BSC/SystemVerilog-SFT-86k
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Updated
21 days ago
•
85.7k
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171
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1
HPAI-BSC/SystemVerilog-RL-12k
RL Environment
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Updated
11 days ago
•
7.77k
•
283
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3
yuhanqin/ut-evaluation
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9 days ago
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174
lumees/hdl-corpus
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Updated
18 days ago
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11.6M
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119
PureOne/saelqir-m1-executable-weight-memory-v1.0
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Updated
16 days ago
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240
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173
xyjoey/VerilogEval-v2-EXT
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Updated
4 days ago
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209
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166