Alpona-1.0-9B

A 9B RTL generation model: Qwen3.5-9B post-trained for SystemVerilog design generation.

This repository holds the complete merged weights โ€” no adapter, no external base to resolve, no checkpoint directories. Download it and it runs.

Results

benchmark pass@1 pass@5
VerilogEval v2 (156 spec-to-RTL tasks) 74.3% 79.2%
RTLLM v2 (50 designs) 66.7% 73.4%

Scored with the official testbenches for each benchmark.

Thinking mode is required

The prompt prefix ends with an open <think>. The chat template in this repo does that for you via add_generation_prompt=True. Scoring an Alpona model with the reasoning block closed costs it a large fraction of its score โ€” do not disable thinking.

Requirements

This is a hybrid architecture (model_type: qwen3_5_text). It will not load on older transformers:

pip install -U "transformers>=5.14.1" torch accelerate

Usage

from transformers import AutoModelForCausalLM, AutoTokenizer

model_id = "musatur/Alpona-1.0-9B"
tok = AutoTokenizer.from_pretrained(model_id)
model = AutoModelForCausalLM.from_pretrained(model_id, dtype="bfloat16", device_map="auto")

messages = [
    {"role": "system", "content": "You are a synthesizable SystemVerilog generation agent. "
                                  "Return only one complete module with the requested interface."},
    {"role": "user", "content": "Design a 4-bit synchronous up counter named TopModule with "
                                "inputs clk, reset and output [3:0] q."},
]
prompt = tok.apply_chat_template(messages, tokenize=False, add_generation_prompt=True)
out = model.generate(**tok(prompt, return_tensors="pt").to(model.device), max_new_tokens=8192)
print(tok.decode(out[0], skip_special_tokens=True))

Licence

other / unresolved-upstream, inherited from the training corpus.

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